1. Field of the Invention
The present invention deals with electrical connection to a circuit inside an integrated circuit that is protected by a seal ring.
2. Background Art
Semiconductor integrated circuits (ICs) are formed on substrates, such as silicon wafers or insulators, and typically comprise a variety of basic electrical components, such as transistors, resistors, capacitors, and the like. The fabricated components are then interconnected using metal layers, and the like. The ICs are formed on the wafer are in repeatable patterns arranged in a grid pattern separated by scribe areas (also called scribe “alleys,” “lanes,” “lines,” “streets,” etc.). Once the wafer is completely processed, it is cut up (also called “diced” or “singulated”) into the individual chips (die). Each die is mounted in a package and the terminals of the die are connected to the package terminals through a wire bonding operation.
It is desirable to verify that such integrated circuit components are fabricated according to a design specification and have certain properties or values, e.g., a specified gain, resistance, capacitance, etc. Such a quality control methodology is referred to as “wafer acceptance testing” or “in-process electrical testing.” It is also desirable to program certain integrated circuit components at the wafer lever before singulation. Probe (or “test”) pads are provided in the scribe lines for both wafer acceptance testing and wafer-level programming.
A metallized “seal ring” is typically formed around the outside of individual chips to isolate and protect them (electrically and/or environmentally). However, the use of seal rings complicates wafer acceptance testing and wafer-level programming. What is needed is a technique to connect the circuits within the chips to the probe pads after the seal ring is implemented.